Field of the Invention
The invention relates to a method of producing a semiconductor body with a first region that has a self-aligning structure, and with a remaining second region. The method includes the following process steps:
applying a first oxide layer to an upper main surface of the semiconductor body, and structuring the first oxide layer; PA1 applying a semiconductor layer to the oxide layer; and PA1 applying an insulation layer to the semiconductor layer. PA1 forming a first oxide layer on an upper main surface of a semiconductor body and structuring the oxide layer; PA1 forming a semiconductor layer on the oxide layer; PA1 forming an insulation layer on the semiconductor layer; PA1 structuring the insulation layer photographically and with subsequent etching such that the insulation layer is fully removed from a second region and remains at least partially on the semiconductor layer in a first region; and PA1 structuring the insulation layer together with the semiconductor layer photographically and with subsequent etching. PA1 implanting a first dopant of a first conductivity type; PA1 implanting a second dopant of a second conductivity type; PA1 applying a further insulation layer surface-wide to the semiconductor body; PA1 structuring the further insulation layer photographically and anisotropically etching down to the semiconductor surface; PA1 anisotropically etching the semiconductor body while using the further insulation layer as a mask; PA1 implanting a third dopant of the second conductivity type while using the further insulation layer as a mask; and PA1 depositing at least one metallization layer on the semiconductor body.
A process of this type is known, for example, from German published, non-prosecuted application DE 44 34 108 A1 (corresponding to commonly assigned U.S. application Ser. No. 08/853,158). The process describes the formation of a low-resistance contact between a metallization layer and a semiconductor material, in which insulator layers with predefined doping and an intermediate semiconductor layer are applied to the surface of the semiconductor material and are structured. Further to this, dopants of different conductivity are implanted in the semiconductor body by using the structured layers as a mask. This gives a small contact area for a given current, and a small turn-on resistance.
The so-called "self-aligning" technique is essential in that process. There, a semiconductor layer, for example heavily doped polycrystalline silicon, is used as the gate material of a MOS transistor, and is at the same time employed as a mask for doping the source and drain (cf. R. Muller: "Bauelemente der Halbleiter-Elektronik" [Semiconductor Electronics Components], Springer-Verlag, Berlin, 1991). In order to structure that semiconductor layer, an at least single-level insulator layer containing a predetermined amount of dopants, is applied to it. The insulator layer serves as a getter layer. The insulator layer may typically be a so-called TEOS which is subsequently structured using a standard photolithographic technique and etched anisotropically. Using the insulator layer as a mask, the semiconductor layer is then etched anisotropically and the desired shape of gate, for example a strip, is produced in the MOS transistor region. A dopant may then be implanted in the semiconductor body through a hole etched into the semiconductor layer.
While the prior art process is very suitable for the production of self-aligning structures in semiconductor bodies, it has been found that problems arise when both power components, for example DMOS transistors, and other components are to be integrated in the semiconductor body. The reason for this is that, in the case of power MOS transistors, for example DMOS transistors, in order to optimize the closing resistance it is necessary to employ the above-mentioned technique with a self-aligning structure which requires the superposition of a semiconductor layer and an overlying insulation layer. This insulation layer which needs to lie on the semiconductor layer is in fact about two times higher than the semiconductor layer. Since the semiconductor layer is also used, in the further region of the semiconductor body where it is not necessary to have a self-aligning structure, in order to produce interconnections, the build-up of the insulation layer on these interconnections which inevitably occurs on account of the above-mentioned production process produces comparatively high steps which further metallization planes must overcome. This entails large interconnection spacings, contact holes on the semiconductor layer, problems with fabrication and yields, and as a result high process costs.
The problem of the high steps which are due to the insulation layer which until now has unavoidably been present on the semiconductor layer, and which further metallization planes need to overcome, is illustrated with the aid of sectional views taken through a part of a semiconductor body produced according to the prior art process. FIGS. 5 to 7 show the semiconductor body in various phases of production.
FIG. 7 illustrates a detail of a finished semiconductor body of this type, in which the region with a self-aligning structure is denoted A and the further region is denoted B. A DMOS transistor is, for example, produced in the region A, while superposed metallization planes for a resistor, a diode or the like are represented summarily in the other region B.
The semiconductor body has a p-doped substrate 10 in which a so-called buried layer 12 is embedded. The buried layer 12 is in the region A. A deep diffusion area 16 which makes a conductive connection between the buried layer 12 and a first metallization layer 32 extends vertically upward from this buried layer 12. To the left of the deep diffusion area 16 there are two p-doped wells 18, only half of the well 18 represented on the left being visible. These p-doped wells 18 are connected centrally to the first metallization layer 32. To the left and to the right of the contact formed on the p-doped well 18 by the metallization layer 32, there are n.sup.+ -doped areas 20 which form the source of a MOS transistor. On the upper main surface of the semiconductor body configured in this way, an oxide layer 22 is disposed which is interrupted by the above-mentioned contacts formed by the metallization layer 32 on the p-doped wells 18 and the deep diffusion area 16. Above the oxide layer 22 there is a semiconductor layer 24 which, for example, may be a heavily doped polysilicon layer. The semiconductor layer 24 is interrupted by the above-mentioned contact with the metallization layer 32 in region A.
In the left-hand part of region A, this semiconductor layer 24 forms the gate electrode layer, on which there is an at least one-level further insulation layer 26. To the left and to the right of the edges of this stack of semiconductor layers 24 and 26, there are so-called spacers 30 which insulatingly cover the edges. The metallization layer 32 extends over the above-mentioned structure. Similarly, the semiconductor layer 24, with the overlying insulation layer 26, is arranged between the p-area 18 represented on the right in FIG. 7 and the deep diffusion area 16. The two-level layer formed by the semiconductor layer 24 and the insulation layer 26 rise in steps to the right.
In the second region B of the semiconductor body, there is likewise provided a structured portion of the above-mentioned semiconductor layer 24, but in this case for producing an interconnection or a resistor rather than a gate electrode. Since, as mentioned above, this semiconductor layer 24 can be structured exclusively via the overlying insulation layer 26 (cf. FIGS. 5 and 6), the latter is necessarily also present in the region B on the semiconductor layer 24. This insulation layer 26 which is necessarily present produces comparatively high steps in region B which are not absolutely necessary because there does not have to be a self-aligning structure in region B for producing MOS transistors, and spacers 30 do not therefore need to be present in this region. Nevertheless, the metallization layer 32 needs to overcome relatively high steps. In order to enable the production of a second interconnection of this type by means of the metallization layer 32 in region B, yet another insulation layer 28 needs to be applied to the semiconductor body (as shown by FIG. 4). Only then can the metallization layer 32 be applied.
For the sake of completeness, there is yet a further upper insulation layer 36 and a second metal layer 34 represented in FIG. 7.
In the fabrication of semiconductor bodies, on which both self-aligning structures and further regions are integrated, the above-mentioned high steps for the metallization layer 32 lead to considerable problems. Indeed, the high steps of the metallization layer, which may for example be an aluminum layer, lead to comparatively deep etching processes. Deep etching processes of this type are expensive and complex in terms of production. Lastly, high steps of this type in the further region of the semiconductor body rule out high packing density of integrated components.